
/* -----------32bit reg tester-------------*/
/*
module test();
	reg iClk, rst;
	reg [1:0] sel;
	reg [31:0] d;
	wire [31:0] q;
	Register_32bit reg1(iClk, 1'b1, d, q, sel[1:0]);

	  initial #400 $finish;
	  initial begin iClk=0; forever #10 iClk=~iClk; end
	    initial fork
		#10 d = 32'h0000001;
		#10 sel[1:0] = 2'b11;
		#50 d = 32'h0000002;
		#50 sel[1:0] = 2'b00;
		#100 sel[1:0] = 2'b11;
		#150 d = 32'h00000003;
		#150 sel[1:0] = 2'b00;
		#180 ;
	    
    
	  join
endmodule
*/
/* instmemory test code 
module test();
	reg iClk, MemWrite;
	reg [6:2] Address;
	reg [31:0] WriteData;
	wire [31:0] ReadData;
	InstMemory i1(iClk, MemWrite, Address, WriteData, ReadData);
	  initial #400 $finish;
	  initial begin iClk=0; forever #10 iClk=~iClk; end
	    initial fork
		#10 MemWrite = 1'b1;
		#10 Address = 5'b00001;
		#10 WriteData = 32'h00000001;
		#30 MemWrite = 1'b0;
		#30 Address = 5'b00001;
		#30 WriteData = 32'h00000001;
		#50 MemWrite = 1'b1;
		#50 Address = 5'b00001;
		#50 WriteData = 32'h00000002;
		#60 MemWrite = 1'b0;
		#150 MemWrite = 1'b0;
		#180 ;
	    
    
	  join
endmodule
*/


module test1();
  reg Clk, Rst;





  
  JWDatapath h1(Clk, Rst);
  initial #300 $finish;
  initial begin Clk=0; forever #5 Clk=~Clk; end
  initial fork
  #1 Rst = 1'b0;
  #2 Rst = 1'b1;
  join
  
endmodule
